Integrated circuit device and electronic instrument

ABSTRACT

An integrated circuit device including first to Nth circuit blocks CB 1  to CBN disposed along a first direction D 1,  when the first direction D 1  is a direction from a first side of the integrated circuit device toward a third side which is opposite to the first side, the first side being a short side, and when a second direction D 2  is a direction from a second side of the integrated circuit device toward a fourth side which is opposite to the second side, the second side being a long side. The circuit blocks CB 1  to CBN include at least one memory block MB which stores image data, and at least one data driver block DB which drives data lines. The memory block MB and the data driver block DB are disposed adjacent to each other along the first direction D 1.

Japanese Patent Application No. 2005-192052, filed on Jun. 30, 2005, ishereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to an integrated circuit device and anelectronic instrument.

A display driver (LCD driver) is an example of an integrated circuitdevice which drives a display panel such as a liquid crystal panel(JP-A-2001-222249). A reduction in the chip size is required for thedisplay driver in order to reduce cost.

However, the size of the display panel incorporated in a portabletelephone or the like is almost constant. Therefore, if the chip size isreduced by merely shrinking the integrated circuit device as the displaydriver by using a macrofabrication technology, it becomes difficult tomount the integrated circuit device.

The type of display panel (amorphous TFT or low-temperature polysiliconTFT) and the number of pixels (QCIF, QVGA, or VGA) are various.Therefore, it is necessary to provide the user with models correspondingto various types of display panels.

Moreover, a change in the layout of the circuit block of the integratedcircuit device affects the remaining circuit blocks, problems such as adecrease in design efficiency and an increase in development periodoccur.

SUMMARY

According to a first aspect of the invention, there is provided anintegrated circuit device, comprising:

first to Nth circuit blocks (N is an integer larger than one) disposedalong a first direction, when the first direction is a direction from afirst side of the integrated circuit device toward a third side which isopposite to the first side, the first side being a short side, and whena second direction is a direction from a second side of the integratedcircuit device toward a fourth side which is opposite to the secondside, the second side being a long side,

wherein the first to Nth circuit blocks include at least one memoryblock which stores image data, and at least one data driver block whichdrives data lines; and

wherein the memory block and the data driver block are disposed adjacentto each other along the first direction.

According to a second aspect of the invention, there is provided anelectronic instrument, comprising:

the above-described integrated circuit device; and

a display panel driven by the integrated circuit device.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

FIGS. 1A, 1B, and 1C are illustrative of a comparative example of oneembodiment of the invention.

FIGS. 2A and 2B are illustrative of mounting of an integrated circuitdevice.

FIG. 3 is a configuration example of an integrated circuit device of theembodiment.

FIG. 4 is an example of various types of display drivers and circuitblocks provided in the display drivers.

FIGS. 5A and 5B are planar layout examples of the integrated circuitdevice of the embodiment.

FIGS. 6A and 6B are examples of cross-sectional diagrams of theintegrated circuit device.

FIG. 7 is a circuit configuration example of the integrated circuitdevice.

FIGS. 8A, 8B, and 8C are illustrative of configuration examples of adata driver and a scan driver.

FIGS. 9A and 9B are configuration examples of a power supply circuit anda grayscale voltage generation circuit.

FIGS. 10A, 10B, and 10C are configuration examples of a D/A conversioncircuit and an output circuit.

FIGS. 11A and 11B are illustrative of a method of disposing a memoryblock and a data driver block adjacent to each other.

FIGS. 12A and 12B are illustrative of a comparative example.

FIGS. 13A and 13B are illustrative of an arrangement of the memory blockand the data driver block.

FIG. 14 is illustrative of a method of reading image data a plurality oftimes in one horizontal scan period.

FIG. 15 is an arrangement example of a data driver and a driver cell.

FIGS. 16A, 16B, and 16C are configuration examples of a memory cell.

FIG. 17 is an arrangement example of the memory block and the drivercell when using a horizontal type cell.

FIG. 18 is an arrangement example of the memory block and the drivercell when using a vertical type cell.

FIGS. 19A and 19B are configuration examples of an electronicinstrument.

DETAILED DESCRIPTION OF THE EMBODIMENT

The invention may provide an integrated circuit device which implementsreduction in circuit area and improvement in design efficiency, and anelectronic instrument including the integrated circuit device.

According to one embodiment of the invention, there is provided anintegrated circuit device, comprising:

first to Nth circuit blocks (N is an integer larger than one) disposedalong a first direction, when the first direction is a direction from afirst side of the integrated circuit device toward a third side which isopposite to the first side, the first side being a short side, and whena second direction is a direction from a second side of the integratedcircuit device toward a fourth side which is opposite to the secondside, the second side being a long side,

wherein the first to Nth circuit blocks include at least one memoryblock which stores image data, and at least one data driver block whichdrives data lines; and

wherein the memory block and the data driver block are disposed adjacentto each other along the first direction.

In the embodiment, the first to Nth circuit blocks are disposed alongthe first direction, and include the memory block and the data driverblock. The memory block and the data driver block are disposed adjacentto each other along the first direction. Therefore, since the width ofthe integrated circuit device in the second direction can be reduced incomparison with a method of disposing the memory block and the datadriver block along the second direction, a slim integrated circuitdevice can be provided. Moreover, when the configuration of the memoryblock or the data driver block is changed, since the effects on othercircuit blocks can be minimized, the design efficiency can be increased.

In this integrated circuit device,

the first to Nth circuit blocks may include:

first to Ith memory blocks (I is an integer larger than one); and

first to Ith data driver blocks respectively disposed adjacent to thefirst to Ith memory blocks along the first direction.

This enables provision of the first to Ith memory blocks in a numberoptimum for the number of bits of the storage target image data and thefirst to Ith data driver blocks corresponding to the first to Ith memoryblocks, for example. Moreover, the width in the second direction and thelength in the first direction of the integrated circuit device can beadjusted by the number of blocks. In particular, the width in the seconddirection can be reduced.

In this integrated circuit device,

when a direction opposite to the first direction is a third direction, aJth data driver block (1≦J<I) among the first to Ith data driver blocksmay be disposed adjacently on the third direction side of a Jth memoryblock among the first to Ith memory blocks;

a (J+1)th memory block among the first to Ith memory blocks may bedisposed adjacently on the first direction side of the Jth memory block;and

a (J+1)th data driver block among the first to Ith data driver blocksmay be disposed adjacently on the first direction side of the (J+1)thmemory block.

In this integrated circuit device, a column address decoder may be usedin common by the Jth memory block and the (J+1)th memory block.

This further reduces the circuit scale.

In this integrated circuit device,

when a direction opposite to the first direction is a third direction, aJth data driver block (1≦J<I) among the first to Ith data driver blocksmay be disposed adjacently on the third direction side of a Jth memoryblock among the first to Ith memory blocks;

a (J+1)th data driver block among the first to Ith data driver blocksmay be disposed adjacently on the first direction side of the Jth memoryblock; and

a (J+1)th memory block among the first to Ith memory blocks may bedisposed adjacently on the first direction side of the (J+1)th datadriver block.

This enables the pitch of the data signal output lines from the first toIth data driver blocks to be made uniform, for example.

In this integrated circuit device,

wordlines connected to a memory cell of the memory block may be disposedalong the second direction in the memory block; and

bitlines through which image data stored in the memory block is outputto the data driver block may be disposed along the first direction inthe memory block.

This enables a signal delay in the wordline to be minimized by reducingthe length of the wordline.

In this integrated circuit device, data signal output lines of the datadriver block may be disposed along the second direction in the datadriver block.

This enables the data signal output line from the data driver block tobe connected with other regions.

In this integrated circuit device, image data stored in the memory blockmay be read from the memory block into the data driver block a pluralityof times in one horizontal scan period.

This enables the width of the memory block in the second direction to bereduced since the number of memory cells of the memory block in thesecond direction is decreased, whereby the width of the integratedcircuit device in the second direction can be reduced.

In this integrated circuit device, the image data stored in the memoryblock may be read a plurality of times in one horizontal scan period byselecting different wordlines in the memory block in one horizontal scanperiod.

In this integrated circuit device, the data driver block may include aplurality of data drivers disposed along the first direction.

This enables various types of data drivers having various configurationsto be efficiently disposed.

In this integrated circuit device,

when the number of pixels of a display panel in a horizontal scandirection is denoted by HPN, the number of bits of image data for onepixel is denoted by PDB, the number of the memory blocks is denoted byMBN, and the number of readings of image data from the memory block inone horizontal scan period is denoted by RN, a sense amplifier block ofthe memory block may include P sense amplifiers arranged along thesecond direction, P being the number of the sense amplifiers given by(HPN×PDB)/(MBN×RN).

This enables the width of the first to Nth circuit blocks in the seconddirection to be set at an optimum width corresponding to the number ofmemory blocks MBN and the number of readings RN of image data.

The integrated circuit device may further comprise:

a first interface region provided along the fourth side and on thesecond direction side of the first to Nth circuit blocks; and

a second interface region provided along the second side and on a fourthdirection side of the first to Nth circuit blocks, the fourth directionbeing opposite to the second direction.

In this integrated circuit device, data signal output lines of the datadriver block may be disposed in the first interface region along thefirst direction.

This enables the data signal output line from the data driver block tobe connected with pads or the like by utilizing the first interfaceregion, whereby a slim integrated circuit device can be provided.

According to one embodiment of the invention, there is provided anelectronic instrument, comprising:

the above described integrated circuit device; and

a display panel driven by the integrated circuit device.

These embodiments of the invention will be described in detail below.Note that the embodiments described below do not in any way limit thescope of the invention laid out in the claims herein. In addition, notall of the elements of the embodiments described below should be takenas essential requirements of the invention.

1. Comparative Example

FIG. 1A shows an integrated circuit device 500 which is a comparativeexample of one embodiment of the invention. The integrated circuitdevice 500 shown in FIG. 1A includes a memory block MB (display dataRAM) and a data driver block DB. The memory block MB and the data driverblock DB are disposed along a direction D2. The memory block MB and thedata driver block DB are ultra-flat blocks of which the length along adirection D1 is longer than the width in the direction D2.

Image data supplied from a host is written into the memory block MB. Thedata driver block DB converts the digital image data written into thememory block MB into an analog data voltage, and drives data lines of adisplay panel. In FIG. 1A, the image data signal flows in the directionD2. Therefore, in the comparative example shown in FIG. 1A, the memoryblock MB and the data driver block DB are disposed along the directionD2 corresponding to the signal flow. This reduces the path between theinput and the output so that a signal delay can be optimized, whereby anefficient signal transmission can be achieved.

However, the comparative example shown in FIG. 1A has the followingproblems.

First, a reduction in the chip size is required for an integratedcircuit device such as a display driver in order to reduce cost.However, if the chip size is reduced by merely shrinking the integratedcircuit device 500 by using a microfabrication technology, the size ofthe integrated circuit device 500 is reduced not only in the short sidedirection but also in the long side direction. Therefore, it becomesdifficult to mount the integrated circuit device 500 as shown in FIG.2A. Specifically, it is desirable that the output pitch be 22 μm ormore, for example. However, the output pitch is reduced to 17 μm bymerely shrinking the integrated circuit device 500 as shown in FIG. 2A,for example, whereby it becomes difficult to mount the integratedcircuit device 500 due to the narrow pitch. Moreover, the number ofglass substrates obtained is decreased due to an increase in the glassframe of the display panel, whereby cost is increased.

Second, the configurations of the memory and the data driver of thedisplay driver are changed corresponding to the type of display panel(amorphous TFT or low-temperature polysilicon TFT), the number of pixels(QCIF, QVGA, or VGA), the specification of the product, and the like.Therefore, in the comparative example shown in FIG. 1A, even if the padpitch, the cell pitch of the memory, and the cell pitch of the datadriver coincide in one product as shown in FIG. 1B, the pitches do notcoincide as shown in FIG. 1C when the configurations of the memory andthe data driver are changed. If the pitches do not coincide as shown inFIG. 1C, an unnecessary interconnect region for absorbing the pitchdifference must be formed between the circuit blocks. In particular, inthe comparative example shown in FIG. 1A in which the block is made flatin the direction D1, the area of an unnecessary interconnect region forabsorbing the pitch difference is increased. As a result, the width W ofthe integrated circuit device 500 in the direction D2 is increased,whereby cost is increased due to an increase in the chip area.

If the layout of the memory and the data driver is changed so that thepad pitch coincides with the cell pitch in order to avoid such aproblem, the development period is increased, whereby cost is increased.Specifically, since the circuit configuration and the layout of eachcircuit block are individually designed and the pitch is adjustedthereafter in the comparative example shown in FIG. 1A, unnecessary areais provided or the design becomes inefficient.

2. Configuration of Integrated Circuit Device

FIG. 3 shows a configuration example of an integrated circuit device 10of one embodiment of the invention which can solve the above-describedproblems. In the embodiment, the direction from a first side SD1 (shortside) of the integrated circuit device 10 toward a third side SD3opposite to the first side SD1 is defined as a first direction D1, andthe direction opposite to the first direction D1 is defined as a thirddirection D3. The direction from a second side SD2 (long side) of theintegrated circuit device 10 toward a fourth side SD4 opposite to thesecond side SD2 is defined as a second direction D2, and the directionopposite to the second direction D2 is defined as a fourth direction D4.In FIG. 3, the left side of the integrated circuit device 10 is thefirst side SD1, and the right side is the third side SD3. However, theleft side may be the third side SD3, and the right side may be the firstside SD1.

As shown in FIG. 3, the integrated circuit device 10 of the embodimentincludes first to Nth circuit blocks CB1 to CBN (N is an integer largerthan one) disposed along the direction D1. Specifically, while thecircuit blocks are arranged in the direction D2 in the comparativeexample shown in FIG. 1A, the circuit blocks CB1 to CBN are arranged inthe direction D1 in the embodiment. Each circuit block is a relativelysquare block differing from the ultra-flat block as in the comparativeexample shown in FIG. 1A.

The integrated circuit device 10 includes an output-side I/F region 12(first interface region in a broad sense) provided along the side SD4and on the D2 side of the first to Nth circuit blocks CB1 to CBN. Theintegrated circuit device 10 includes an input-side I/F region 14(second interface region in a broad sense) provided along the side SD2and on the D4 side of the first to Nth circuit blocks CB1 to CBN. Inmore detail, the output-side I/F region 12 (first I/O region) isdisposed on the D2 side of the circuit blocks CB1 to CBN without othercircuit blocks interposed therebetween, for example. The input-side I/Fregion 14 (second I/O region) is disposed on the D4 side of the circuitblocks CB1 to CBN without other circuit blocks interposed therebetween,for example. Specifically, only one circuit block (data driver block)exists in the direction D2 at least in the area in which the data driverblock exists. When the integrated circuit device 10 is used as anintellectual property (IP) core and incorporated in another integratedcircuit device, the integrated circuit device 10 may be configured toexclude at least one of the I/F regions 12 and 14.

The output-side (display panel side) I/F region 12 is a region whichserves as an interface between the integrated circuit device 10 and thedisplay panel, and includes pads and various elements such as outputtransistors and protective elements connected with the pads. In moredetail, the output-side I/F region 12 includes output transistors foroutputting data signals to data lines and scan signals to scan lines,for example. When the display panel is a touch panel, the output-sideI/F region 12 may include input transistors.

The input-side I/F region 14 is a region which serves as an interfacebetween the integrated circuit device 10 and a host (MPU, imageprocessing controller, or baseband engine), and may include pads andvarious elements connected with the pads, such as input (input-output)transistors, output transistors, and protective elements. In moredetail, the input-side I/F region 14 includes input transistors forinputting signals (digital signals) from the host, output transistorsfor outputting signals to the host, and the like.

An output-side or input-side I/F region may be provided along the shortside SD1 or SD3. Bumps which serve as external connection terminals maybe provided in the I/F (interface) regions 12 and 14, or may be providedin other regions (first to Nth circuit blocks CB1 to CBN). Whenproviding the bumps in the region other than the I/F regions 12 and 14,the bumps are formed by using a small bump technology (e.g. bumptechnology using resin core) other than a gold bump technology.

The first to Nth circuit blocks CB1 to CBN may include at least two (orthree) different circuit blocks (circuit blocks having differentfunctions). Taking an example in which the integrated circuit device 10is a display driver, the circuit blocks CB1 to CBN may include at leasttwo of a data driver block, a memory block, a scan driver block, a logiccircuit block, a grayscale voltage generation circuit block, and a powersupply circuit block. In more detail, the circuit blocks CB1 to CBN mayinclude at least a data driver block and a logic circuit block, and mayfurther include a grayscale voltage generation circuit block. When theintegrated circuit device 10 includes a built-in memory, the circuitblocks CB1 to CBN may further include a memory block.

FIG. 4 shows an example of various types of display drivers and circuitblocks provided in the display drivers. In an amorphous thin filmtransistor (TFT) panel display driver including a built-in memory (RAM),the circuit blocks CB1 to CBN include a memory block, a data driver(source driver) block, a scan driver (gate driver) block, a logiccircuit (gate array circuit) block, a grayscale voltage generationcircuit (?-correction circuit) block, and a power supply circuit block.In a low-temperature polysilicon (LTPS) TFT panel display driverincluding a built-in memory, since the scan driver can be formed on aglass substrate, the scan driver block may be omitted. The memory blockmay be omitted in an amorphous TFT panel display driver which does notinclude a memory, and the memory block and the scan driver block may beomitted in a low-temperature polysilicon TFT panel display driver whichdoes not include a memory. In a color super twisted nematic (CSTN) paneldisplay driver and a thin film diode (TFD) panel display driver, thegrayscale voltage generation circuit block may be omitted.

FIGS. 5A and 5B show examples of a planar layout of the integratedcircuit device 10 as the display driver of the embodiment. FIGS. 5A and5B are examples of an amorphous TFT panel display driver including abuilt-in memory. FIG. 5A shows a QCIF and 32-grayscale display driver,and FIG. 5B shows a QVGA and 64-grayscale display driver.

In FIGS. 5A and 5B, the first to Nth circuit blocks CB1 to CBN includefirst to fourth memory blocks MB1 to MB4 (first to Ith memory blocks ina broad sense; I is an integer larger than one). The first to Nthcircuit blocks CB1 to CBN include first to fourth data driver blocks DB1to DB4 (first to Ith data driver blocks in a broad sense) respectivelydisposed adjacent to the first to fourth memory blocks MB1 to MB4 alongthe direction D1. In more detail, the memory block MB1 and the datadriver block DB1 are disposed adjacent to each other along the directionD1, and the memory block MB2 and the data driver block DB2 are disposedadjacent to each other along the direction D1. The memory block MB1adjacent to the data driver block DB1 stores image data (display data)used by the data driver block DB1 to drive the data line, and the memoryblock MB2 adjacent to the data driver block DB2 stores image data usedby the data driver block DB2 to drive the data line.

In FIG. 5A, the data driver block DB1 (Jth data driver block in a broadsense; 1≦J<I) of the data driver blocks DB1 to DB4 is disposedadjacently on the D3 side of the memory block MB1 (Jth memory block in abroad sense) of the memory blocks MB1 to MB4. The memory block MB2((J+1)th memory block in a broad sense) is disposed adjacently on the D1side of the memory block MB1. The data driver block DB2 ((J+1)th datadriver block in a broad sense) is disposed adjacently on the D1 side ofthe memory block MB2. The arrangement of the memory blocks MB3 and MB4and the data driver blocks DB3 and DB4 is the same as described above.In FIG. 5A, the memory block MB1 and the data driver block DB1 and thememory block MB2 and the data driver block DB2 are disposedline-symmetrical with respect to the borderline between the memoryblocks MB1 and MB2, and the memory block MB3 and the data driver blockDB3 and the memory block MB4 and the data driver block DB4 are disposedline-symmetrical with respect to the borderline between the memoryblocks MB3 and MB4. In FIG. 5A, the data driver blocks DB2 and DB3 aredisposed adjacent to each other. However, another circuit block may bedisposed between the data driver blocks DB2 and DB3.

In FIG. 5B, the data driver block DB1 (Jth data driver block) of thedata driver blocks DB1 to DB4 is disposed adjacently on the D3 side ofthe memory block MB1 (Jth memory block) of the memory blocks MB1 to MB4.The data driver block DB2 ((J+1)th data driver block) is disposed on theD1 side of the memory block MB1. The memory block MB2 ((J+1)th memoryblock) is disposed on the D1 side of the data driver block DB2. The datadriver block DB3, the memory block MB3, the data driver block DB4, andthe memory block MB4 are disposed in the same manner as described above.In FIG. 5B, the memory block MB1 and the data driver block DB2, thememory block MB2 and the data driver block DB3, and the memory block MB3and the data driver block DB4 are respectively disposed adjacent to eachother. However, another circuit block may be disposed between theseblocks.

The layout arrangement shown in FIG. 5A has an advantage in that acolumn address decoder can be used in common between the memory blocksMB1 and MB2 or the memory blocks MB3 and MB4 (between the Jth and(J+1)th memory blocks). The layout arrangement shown in FIG. 5B has anadvantage in that the interconnect pitch of the data signal output linesfrom the data driver blocks DB1 to DB4 to the output-side I/F region 12can be equalized so that the interconnect efficiency can be increased.

The layout arrangement of the integrated circuit device 10 of theembodiment is not limited to those shown in FIGS. 5A and 5B. Forexample, the number of memory blocks and data driver blocks may be setat 2, 3, or 5 or more, or the memory block and the data driver block maynot be divided into blocks. A modification in which the memory block isnot disposed adjacent to the data driver block is also possible. Aconfiguration is also possible in which the memory block, the scandriver block, the power supply circuit block, or the grayscale voltagegeneration circuit block is not provided. A circuit block having a widthsignificantly small in the direction D2 (narrow circuit block having awidth less than the width WB) may be provided between the circuit blocksCB1 to CBN and the output-side I/F region 12 or the input-side I/Fregion 14. The circuit blocks CB1 to CBN may include a circuit block inwhich different circuit blocks are arranged in stages in the directionD2. For example, the scan driver circuit and the power supply circuitmay be formed in one circuit block.

FIG. 6A shows an example of a cross-sectional diagram of the integratedcircuit device 10 of the embodiment along the direction D2. W1, WB, andW2 respectively indicate the widths of the output-side I/F region 12,the circuit blocks CB1 to CBN, and the input-side I/F region 14 in thedirection D2. W indicates the width of the integrated circuit device 10in the direction D2.

In the embodiment, as shown in FIG. 6A, a configuration may be employedin which a circuit blocks is not provided between the circuit blocks CB1to CBN (data driver block DB) and the output-side I/F region 12 orinput-side I/F region 14. Therefore, the relationship“W1+WB+W2≦W<W1+2×WB+W2” is satisfied so that a slim integrated circuitdevice can be realized. In more detail, the width W in the direction D2may be set at “W<2 mm”. More specifically, the width W in the directionD2 may be set at “W<1.5 mm”. It is preferable that “W>0.9 mm” takinginspection and mounting of the chip into consideration. A length LD inthe long side direction may be set at “15 mm<LD<27 mm”. A chip shaperatio SP (=LD/W) may be set at “SP>10”. More specifically, the chipshape ratio SP may be set at “SP>12”.

The widths W1, WB, and W2 shown in FIG. 6A indicate the widths oftransistor formation regions (bulk regions or active regions) of theoutput-side I/F region 12, the circuit blocks CB1 to CBN, and theinput-side I/F region 14, respectively. Specifically, outputtransistors, input transistors, input-output transistors, transistors ofelectrostatic protection elements, and the like are formed in the I/Fregions 12 and 14. Transistors which form circuits are formed in thecircuit blocks CB1 to CBN. The widths W1, WB, and W2 are determinedbased on well regions and diffusion regions by which such transistorsare formed. In order to realize a slim integrated circuit device, it ispreferable to form bumps (active surface bumps) on the transistors ofthe circuit blocks CB1 to CBN. In more detail, a resin core bump inwhich the core is formed of a resin and a metal layer is formed on thesurface of the resin or the like is formed above the transistor (activeregion). These bumps (external connection terminals) are connected withthe pads disposed in the I/F regions 12 and 14 through metalinterconnects. The widths W1, WB, and W2 of the embodiment are not thewidths of the bump formation regions, but the widths of the transistorformation regions formed under the bumps.

The widths of the circuit blocks CB1 to CBN in the direction D2 may beidentical, for example. In this case, it suffices that the width of eachcircuit block be substantially identical, and the width of each circuitblock may differ in the range of several to 20 μm (several tens ofmicrons), for example. When a circuit block with a different widthexists in the circuit blocks CB1 to CBN, the width WB may be the maximumwidth of the circuit blocks CB1 to CBN. In this case, the maximum widthmay be the width of the data driver block in the direction D2, forexample. In the case where the integrated circuit device includes amemory, the maximum width may be the width of the memory block in thedirection D2. A vacant region having a width of about 20 to 30 μm may beprovided between the circuit blocks CB1 to CBN and the I/F regions 12and 14, for example.

In the embodiment, a pad of which the number of stages in the directionD2 is one or more may be disposed in the output-side I/F region 12.Therefore, the width W1 of the output-side I/F region 12 in thedirection D2 may be set at “0.13 mm≦W1≦0.4 mm” taking the pad width(e.g. 0.1 mm) and the pad pitch into consideration. Since a pad of whichthe number of stages in the direction D2 is one can be disposed in theinput-side I/F region 14, the width W2 of the input-side I/F region 14may be set at “0.1 mm≦W2≦0.2 mm”. In order to realize a slim integratedcircuit device, interconnects for logic signals from the logic circuitblock, grayscale voltage signals from the grayscale voltage generationcircuit block, and a power supply must be formed on the circuit blocksCB1 to CBN by using global interconnects. The total width of theseinterconnects is about 0.8 to 0.9 mm, for example. Therefore, the widthsWB of the circuit blocks CB1 to CBN may be set at “0.65 mm≦WB≦1.2 mm”taking the total width of these interconnects into consideration.

Since “0.65 mm≦WB≦1.2 mm” is satisfied even if W1=0.4 mm and W2=0.2 mm,WB>W1+W2 is satisfied. When the widths W1, WB, and W2 are minimumvalues, W1=0.13 mm, WB=0.65 mm, and W2=0.1 mm so that the width W of theintegrated circuit device is about 0.88 mm. Therefore, “W=0.88mm<2×WB=1.3 mm” is satisfied. When the widths W1, WB, and W2 are maximumvalues, W1=0.4 mm, WB=1.2 mm, and W2=0.2 mm so that the width W of theintegrated circuit device is about 1.8 mm. Therefore, “W=1.8 mm<2×WB=2.4mm” is satisfied. Therefore, the relational equation “W<2×WB” issatisfied so that a slim integrated circuit device is realized.

In the comparative example shown in FIG. 1A, two or more circuit blocksare disposed along the direction D2 as shown in FIG. 6B. Moreover,interconnect regions are formed between the circuit blocks and betweenthe circuit blocks and the I/F region in the direction D2. Therefore,since the width W of the integrated circuit device 500 in the directionD2 (short side direction) is increased, a slim chip cannot be realized.Therefore, even if the chip is shrunk by using a macrofabricationtechnology, the length LD in the direction D1 (long side direction) isdecreased, as shown in FIG. 2A, so that the output pitch becomes narrow,whereby it becomes difficult to mount the integrated circuit device 500.

In the embodiment, the circuit blocks CB1 to CBN are disposed along thedirection D1 as shown in FIGS. 3, 5A, and 5B. As shown in FIG. 6A, thetransistor (circuit element) can be disposed under the pad (bump)(active surface bump). Moreover, the signal lines can be formed betweenthe circuit blocks and between the circuit blocks and the I/F by usingthe global interconnects formed in the upper layer (lower layer of thepad) of the local interconnects in the circuit blocks. Therefore, sincethe width W of the integrated circuit device 10 in the direction D2 canbe reduced while maintaining the length LD of the integrated circuitdevice 10 in the direction D1 as shown in FIG. 2B, a very slim chip canbe realized. As a result, since the output pitch can be maintained at 22μm or more, for example, mounting can be facilitated.

In the embodiment, since the circuit blocks CB1 to CBN are disposedalong the direction D1, it is possible to easily deal with a change inthe product specifications and the like. Specifically, since product ofvarious specifications can be designed by using a common platform, thedesign efficiency can be increased. For example, when the number ofpixels or the number of grayscales of the display panel is increased ordecreased in FIGS. 5A and 5B, it is possible to deal with such asituation merely by increasing or decreasing the number of blocks ofmemory blocks or data driver blocks, the number of readings of imagedata in one horizontal scan period, or the like. FIGS. 5A and 5B show anexample of an amorphous TFT panel display driver including a memory.When developing a low-temperature polysilicon TFT panel productincluding a memory, it suffices to remove the scan driver block from thecircuit blocks CB1 to CBN. When developing a product which does notinclude a memory, it suffices to remove the memory block from thecircuit blocks CB1 to CBN. In the embodiment, even if the circuit blockis removed corresponding to the specification, since the effect on theremaining circuit blocks is minimized, the design efficiency can beincreased.

In the embodiment, the widths (heights) of the circuit blocks CB1 to CBNin the direction D2 can be uniformly adjusted to the width (height) ofthe data driver block or the memory block, for example. Since it ispossible to deal with an increase or decrease in the number oftransistors of each circuit block by increasing or decreasing the lengthof each circuit block in the direction D1, the design efficiency can befurther increased. For example, when the number of transistors isincreased or decreased in FIGS. 5A and 5B due to a change in theconfiguration of the grayscale voltage generation circuit block or thepower supply circuit block, it is possible to deal with such a situationby increasing or decreasing the length of the grayscale voltagegeneration circuit block or the power supply circuit block in thedirection D1.

As a second comparative example, a narrow data driver block may bedisposed in the direction D1, and other circuit blocks such as thememory block may be disposed along the direction D1 on the D4 side ofthe data driver block, for example. However, in the second comparativeexample, since the data driver block having a large width lies betweenother circuit blocks such as the memory block and the output-side I/Fregion, the width W of the integrated circuit device in the direction D2is increased, so that it is difficult to realize a slim chip. Moreover,an additional interconnect region is formed between the data driverblock and the memory block, whereby the width W is further increased.Furthermore, when the configuration of the data driver block or thememory block is changed, the pitch difference described with referenceto FIGS. 1B and 1C occurs, whereby the design efficiency cannot beincreased.

As a third comparative example of the embodiment, only circuit blocks(e.g. data driver blocks) having the same function may be divided andarranged in the direction D1. However, since the integrated circuitdevice can be provided with only a single function (e.g. function of thedata driver) in the third comparative example, development of variousproducts cannot be realized. In the embodiment, the circuit blocks CB1to CBN include circuit blocks having at least two different functions.Therefore, various integrated circuit devices corresponding to varioustypes of display panels can be provided as shown in FIGS. 4, 5A, and 5B.

3. Circuit Configuration

FIG. 7 shows a circuit configuration example of the integrated circuitdevice 10. The circuit configuration of the integrated circuit device 10is not limited to the circuit configuration shown in FIG. 7. Variousmodifications and variations may be made. A memory 20 (display data RAM)stores image data. A memory cell array 22 includes a plurality of memorycells, and stores image data (display data) for at least one frame (onescreen). In this case, one pixel is made up of R, G, and B subpixels(three dots), and 6-bit (k-bit) image data is stored for each subpixel,for example. A row address decoder 24 (MPU/LCD row address decoder)decodes a row address and selects a wordline of the memory cell array22. A column address decoder 26 (MPU column address decoder) decodes acolumn address and selects a bitline of the memory cell array 22. Awrite/read circuit 28 (MPU write/read circuit) writes image data intothe memory cell array 22 or reads image data from the memory cell array22. An access region of the memory cell array 22 is defined by arectangle having a start address and an end address as oppositevertices. Specifically, the access region is defined by the columnaddress and the row address of the start address and the column addressand the row address of the end address so that memory access isperformed.

A logic circuit 40 (e.g. automatic placement and routing circuit)generates a control signal for controlling display timing, a controlsignal for controlling data processing timing, and the like. The logiccircuit 40 may be formed by automatic placement and routing such as agate array (G/A). A control circuit 42 generates various control signalsand controls the entire device. In more detail, the control circuit 42outputs grayscale characteristic (?-characteristic) adjustment data(?-correction data) to a grayscale voltage generation circuit 110 andcontrols voltage generation of a power supply circuit 90. The controlcircuit 42 controls write/read processing for the memory using the rowaddress decoder 24, the column address decoder 26, and the write/readcircuit 28. A display timing control circuit 44 generates variouscontrol signals for controlling display timing, and controls reading ofimage data from the memory into the display panel. A host (MPU)interface circuit 46 realizes a host interface which accesses the memoryby generating an internal pulse each time accessed by the host. An RGBinterface circuit 48 realizes an RGB interface which writes motionpicture RGB data into the memory based on a dot clock signal. Theintegrated circuit device 10 may be configured to include only one ofthe host interface circuit 46 and the RGB interface circuit 48.

In FIG. 7, the host interface circuit 46 and the RGB interface circuit48 access the memory 20 in pixel units. Image data designated by a lineaddress and read in line units is supplied to a data driver 50 in linecycle at an internal display timing independent of the host interfacecircuit 46 and the RGB interface circuit 48.

The data driver 50 is a circuit for driving a data line of the displaypanel. FIG. 8A shows a configuration example of the data driver 50. Adata latch circuit 52 latches the digital image data from the memory 20.A D/A conversion circuit 54 (voltage select circuit) performs D/Aconversion of the digital image data latched by the data latch circuit52, and generates an analog data voltage. In more detail, the D/Aconversion circuit 54 receives a plurality of (e.g. 64 stages) grayscalevoltages (reference voltages) from the grayscale voltage generationcircuit 110, selects a voltage corresponding to the digital image datafrom the grayscale voltages, and outputs the selected voltage as thedata voltage. An output circuit 56 (driver circuit or buffer circuit)buffers the data voltage from the D/A conversion circuit 54, and outputsthe data voltage to the data line of the display panel to drive the dataline. A part of the output circuit 56 (e.g. output stage of operationalamplifier) may not be included in the data driver 50 and may be disposedin other region.

A scan driver 70 is a circuit for driving a scan line of the displaypanel. FIG. 8B shows a configuration example of the scan driver 70. Ashift register 72 includes a plurality of sequentially connectedflip-flops, and sequentially shifts an enable input-output signal EIO insynchronization with a shift clock signal SCK. A level shifter 76converts the voltage level of the signal from the shift register 72 intoa high voltage level for selecting the scan line. An output circuit 78buffers a scan voltage converted and output by the level shifter 76, andoutputs the scan voltage to the scan line of the display panel to drivethe scan line. The scan driver 70 may be configured as shown in FIG. 8C.In FIG. 8C, a scan address generation circuit 73 generates and outputs ascan address, and an address decoder decodes the scan address. The scanvoltage is output to the scan line specified by the decode processingthrough the level shifter 76 and the output circuit 78.

The power supply circuit 90 is a circuit which generates various powersupply voltages. FIG. 9A shows a configuration example of the powersupply circuit 90. A voltage booster circuit 92 is a circuit whichgenerates a boosted voltage by boosting an input power source voltage oran internal power supply voltage by a charge-pump method using a boostcapacitor and a boost transistor, and may include first to fourthvoltage booster circuits and the like. A high voltage used by the scandriver 70 and the grayscale voltage generation circuit 110 can begenerated by the voltage booster circuit 92. A regulator circuit 94regulates the level of the boosted voltage generated by the voltagebooster circuit 92. A VCOM generation circuit 96 generates and outputs avoltage VCOM supplied to a common electrode of the display panel. Acontrol circuit 98 controls the power supply circuit 90, and includesvarious control registers and the like.

The grayscale voltage generation circuit 110 (?-correction circuit) is acircuit which generates grayscale voltages. FIG. 9B shows aconfiguration example of the grayscale voltage generation circuit 110. Aselect voltage generation circuit 112 (voltage divider circuit) outputsselect voltages VS0 to VS255 (R select voltages in a broad sense) basedon high-voltage power supply voltages VDDH and VSSH generated by thepower supply circuit 90. In more detail, the select voltage generationcircuit 112 includes a ladder resistor circuit including a plurality ofresistor elements connected in series. The select voltage generationcircuit 112 outputs voltages obtained by dividing the power supplyvoltages VDDH and VSSH using the ladder resistor circuit as the selectvoltages VS0 to VS255. A grayscale voltage select circuit 114 selects 64(S in a broad sense; R>S) voltages from the select voltages VS0 to VS255in the case of using 64 grayscales based on the grayscale characteristicadjustment data set in an adjustment register 116 by the logic circuit40, and outputs the selected voltages as grayscale voltages V0 to V63.This enables generation of a grayscale voltage having grayscalecharacteristics (?-correction characteristics) optimum for the displaypanel. In the case of performing a polarity reversal drive, a positiveladder resistor circuit and a negative ladder resistor circuit may beprovided in the select voltage generation circuit 112. The resistancevalue of each resistor element of the ladder resistor circuit may bechanged based on the adjustment data set in the adjustment register 116.An impedance conversion circuit (voltage-follower-connected operationalamplifier) may be provided in the select voltage generation circuit 112or the grayscale voltage select circuit 114.

FIG. 10A shows a configuration example of a digital-analog converter(DAC) included in the D/A conversion circuit 54 shown in FIG. 8A. TheDAC shown in FIG. 10A may be provided in subpixel units (or pixelunits), and may be formed by a ROM decoder and the like. The DAC selectsone of the grayscale voltages V0 to V63 from the grayscale voltagegeneration circuit 110 based on 6-bit digital image data D0 to D5 andinverted data XD0 to XD5 from the memory 20 to convert the image data D0to D5 into an analog voltage. The DAC outputs the resulting analogvoltage signal DAQ (DAQR, DAQG, DAQB) to the output circuit 56.

When R, G, and B data signals are multiplexed and supplied to alow-temperature polysilicon TFT display driver or the like (FIG. 10C),R, G, and B image data may be D/A converted by using one common DAC. Inthis case, the DAC shown in FIG. 10A is provided in pixel units.

FIG. 10B shows a configuration example of an output section SQ includedin the output circuit 56 shown in FIG. 8A. The output section SQ shownin FIG. 10B may be provided in pixel units. The output section SQincludes R (red), G (green), and B (blue) impedance conversion circuitsOPR, OPG, and OPB (voltage-follower-connected operational amplifiers),performs impedance conversion of the signals DAQR, DAQG, and DAQB fromthe DAC, and outputs data signals DATAR, DATAG, and DATAB to R, G, and Bdata signal output lines. When using a low-temperature polysilicon TFTpanel, switch elements (switch transistors) SWR, SWG, and SWB as shownin FIG. 10C may be provided, and the impedance conversion circuit OP mayoutput a data signal DATA in which the R, G, and B data signals aremultiplexed. The data signals may be multiplexed over a plurality ofpixels. Only the switch elements and the like may be provided in theoutput section SQ without providing the impedance conversion circuit asshown in FIGS. 10B and 10C.

4. Adjacency of Data Driver Block and Memory Block

In the embodiment, the data driver block DB and the memory block MB aredisposed adjacent to each other in the direction D1, as shown in FIG.11A.

In the comparative example shown in FIG. 1A, the memory block MB and thedata driver block DB are disposed along the direction D2 (short sidedirection) corresponding to the signal flow, as shown in FIG. 12A.Therefore, since the width of the integrated circuit device in thedirection D2 is increased, it is difficult to realize a slim chip.Moreover, when the number of pixels of the display panel, thespecification of the display driver, the configuration of the memorycell, or the like is changed so that the width in the direction D2 orthe length in the direction D1 of the memory block MB or the data driverblock DB is changed, the remaining circuit blocks are affected by such achange, whereby the design efficiency is decreased.

In the embodiment, since the data driver block DB and the memory blockMB are disposed along the direction D1, the width W of the integratedcircuit device in the direction D2 can be reduced, whereby a very slimchip as shown in FIG. 2B can be realized. Moreover, since it is possibleto deal with a change in the number of pixels of the display panel orthe like by dividing the memory block as shown in FIG. 11B, the designefficiency can be increased.

In FIG. 12A, since the wordline WL is disposed along the direction D1(long side direction), a signal delay in the wordline WL is increased,whereby the image data read speed is decreased. In particular, since thewordline WL connected with the memory cells is formed by a polysiliconlayer, the signal delay problem is serious. In this case, buffercircuits 520 and 522 as shown in FIG. 12B may be provided in order toreduce the signal delay. However, use of this method increases thecircuit scale so that cost is increased.

In the embodiment, the wordline WL is disposed in the memory block MBalong the direction D2 (short side direction), and the bitline BL isdisposed along the direction D1 (long side direction), as shown in FIG.11A. In the embodiment, the width W of the integrated circuit device inthe direction D2 is small. Therefore, since the length of the wordlineWL in the memory block MB can be reduced, a signal delay in the wordlineWL can be significantly reduced in comparison with the comparativeexample shown in FIG. 12A. Moreover, since it is unnecessary to providethe buffer circuits 520 and 522 as shown in FIG. 12B, the circuit areacan be reduced. In the comparative example shown in FIG. 12A, since thewordline WL, which is long in the direction D1 and has a large parasiticcapacitance, is selected even when a part of the access region of thememory is accessed by the host, power consumption is increased. On theother hand, according to the method of dividing the memory into blocksin the direction D1 as shown in FIG. 11B, since only the wordline WL ofthe memory block corresponding to the access region accessed by the hostis selected, a reduction in power consumption can be realized.

The wordline WL shown in FIG. 11A is a wordline connected with thememory cells of the memory block MB. Specifically, the wordline WL shownin FIG. 11A is a local wordline connected with a gate of a transfertransistor of the memory cell. The BL bitline shown in FIG. 11A is abitline through which image data (data signal) stored in the memoryblock MB (memory cell array) is output to the data driver block DB.Specifically, the signal of image data stored in the memory block MB isoutput from the memory block MB to the data driver block DB in thedirection along the bitline BL.

The method of disposing the memory block MB and the data driver block DBalong the direction D2 as in the comparative example shown in FIG. 12 isreasonable taking the signal flow into consideration.

In the embodiment, the output line DQL of the data signal from the datadriver block DB is disposed in the data driver block DB along thedirection D2, as shown in FIG. 11A. On the other hand, the data signaloutput line DQL is disposed in the output-side I/F region 12 (firstinterface region) along the direction D1 (D3). In more detail, the datasignal output line DQL is disposed in the output-side I/F region 12along the direction D1 by using the global interconnect which is locatedin the lower layer of the pad and in the upper layer of the localinterconnect (transistor interconnect) in the output-side I/F region 12.This enables the data signal from the data driver block DB to beproperly output to the display panel through the pad, even when the datadriver block DB and the memory block MB are disposed in the directionD1. Moreover, if the data signal output line DQL is disposed as shown inFIG. 11A, the data signal output line DQL can be connected with the pador the like by utilizing the output-side I/F region 12, whereby anincrease in the width W of the integrated circuit device in thedirection D2 can be prevented.

5. Details of Memory Block and Data Driver Block

5.1 Block Division

Suppose that the display panel is a QVGA panel in which the number ofpixels VPN in the vertical scan direction (data line direction) is 320and the number of pixels HPN in the horizontal scan direction (scan linedirection) is 240, as shown in FIG. 13A. Suppose that the number of bitsPDB of image (display) data for one pixel is 18 bits (six bits each forR, G, and B). In this case, the number of bits of image data necessaryfor displaying one frame of the display panel is“VPN×HPN×PDB=320×240×18” bits. Therefore, the memory of the integratedcircuit device stores at least “320×240×18” bits of image data. The datadriver outputs data signals for HPN=240 data lines (data signalscorresponding to 240×18 bits of image data) to the display panel in onehorizontal scan period (period in which one scan line is scanned).

In FIG. 13B, the data driver is divided into four (DBN=4) data driverblocks DB1 to DB4. The memory is also divided into four (MBN=DBN=4)memory blocks MB1 to MB4. Therefore, each of the data driver blocks DB1to DB4 outputs data signals for 60 (HPN/DBN=240/4=60) data lines to thedisplay panel in one horizontal scan period. Each of the memory blocksMB1 to MB4 stores image data for “(VPN×HPN×PDB)/MBN=(320×240×18)/4”bits.

In the embodiment, a column address decoder CD12 is used in common bythe memory blocks MB1 and MB2, as shown in FIG. 13B. A column addressdecoder CD34 is used in common by the memory blocks MB3 and MB4. In thecomparative example shown in FIG. 12A, since the column address decoderis disposed on the D4 side of the memory cell array, the column addressdecoder cannot be used in common as shown in FIG. 13B. In theembodiment, since the column address decoders CD12 and CD34 can be usedin common, a reduction in the circuit area and a reduction in cost canbe achieved. When the data driver blocks DB1 to DB4 and the memoryblocks MB1 to MB4 are disposed as shown in FIG. 5B, the column addressdecoder cannot be used in common. However, the pitch of the data signallines from the data driver block can be made uniform in FIG. 5B, wherebyrouting of the interconnect can be facilitated.

5.2 A Plurality of Readings in One Horizontal Scan Period

In FIG. 13B, each of the data driver blocks DB1 to DB4 outputs datasignals for 60 data lines in one horizontal scan period. Therefore,image data corresponding to the data signals for 240 data lines must beread from the data driver blocks DB1 to DB4 corresponding to the datadriver blocks DB1 to DB4 in one horizontal scan period.

However, when the number of bits of image data read in one horizontalscan period is increased, it is necessary to increase the number ofmemory cells (sense amplifiers) arranged in the direction D2. As aresult, since the width W of the integrated circuit device in thedirection D2 is increased, the width of the chip cannot be reduced.Moreover, since the length of the wordline WL is increased, a signaldelay problem in the wordline WL occurs.

In the embodiment, the image data stored in the memory blocks MB1 to MB4is read from the memory blocks MB1 to MB4 into the data driver blocksDB1 to DB4 a plurality of times (RN times) in one horizontal scanperiod.

In FIG. 14, a memory access signal MACS (word select signal) goes active(high level) twice (RN=2) in one horizontal scan period as indicated byA1 and A2, for example. This causes the image data to be read from eachmemory block into each data driver block twice (RN=2) in one horizontalscan period. Then, data latch circuits included in data drivers DRa andDRb shown in FIG. 15 provided in the data driver block latch the readimage data based on latch signals LATa and LATb indicated by A3 and A4.D/A conversion circuits included in the data drivers DRa and DRb performD/A conversion of the latched image data, and output circuits includedin the data drivers DRa and DRb output data signals DATAa and DATAbobtained by D/A conversion to the data signal output line as indicatedby A5 and A6. A scan signal SCSEL input to the gate of the TFT of eachpixel of the display panel goes active as indicated by A7, and the datasignal is input to and held by each pixel of the display panel.

In FIG. 14, the image data is read twice in the first horizontal scanperiod, and the data signals DATAa and DATAb are output to the datasignal output line in the first horizontal scan period. However, theimage data may be read twice and latched in the first horizontal scanperiod, and the data signals DATAa and DATAb corresponding to thelatched image data may be output to the data signal output line in thesecond horizontal scan period. FIG. 14 shows the case where the numberof readings RN is 2. However, the number of readings RN may be three ormore (RN≧3).

According to the method shown in FIG. 14, the image data correspondingto the data signals for 30 data lines is read from each memory block,and each of the data drivers DRa and DRb outputs the data signals for 30data lines, as shown in FIG. 15. Therefore, the data signals for 60 datalines are output from each data driver block. As described above, itsuffices to read the image data corresponding to the data signals for 30data lines from each memory block in one read operation in FIG. 14.Therefore, the number of memory cells and sense amplifiers in thedirection D2 in FIG. 15 can be reduced in comparison with the method ofreading the image data only once in one horizontal scan period. As aresult, since the width W of the integrated circuit device in thedirection D2 can be reduced, a very slim chip as shown in FIG. 2B can berealized. The length of one horizontal scan period is about 52microseconds in the case of a QVGA display. On the other hand, thememory read time is about 40 nsec, for example, which is sufficientlyshorter than 52 microseconds. Therefore, even if the number of readingsin one horizontal scan period is increased from once to several times,the display characteristics are not affected to a large extent.

FIG. 13A shows an example of a QVGA (320×240) display panel. However, itis possible to deal with a VGA (640×480) display panel by increasing thenumber of readings RN in one horizontal scan period to four (RN=4), forexample, whereby the degrees of freedom of the design can be increased.

A plurality of readings in one horizontal scan period may be realized bya first method in which the row address decoder (wordline selectcircuit) selects different wordlines in each memory block in onehorizontal scan period, or a second method in which the row addressdecoder (wordline select circuit) selects a single wordline in eachmemory block a plurality of times in one horizontal scan period. Or, aplurality of readings in one horizontal scan period may be realized bycombining the first method and the second method.

5.3 Arrangement of Data Driver and Driver Cell

FIG. 15 shows an arrangement example of data drivers and driver cellsincluded in the data drivers. As shown in FIG. 15, the data driver blockincludes a plurality of data drivers DRa and DRb (first to mth datadrivers) disposed along the direction D1. Each of the data drivers DRaand DRb includes 30 (Q in a broad sense) driver cells DRC1 to DRC30.

When a wordline WL1 a of the memory block is selected and the firstimage data is read from the memory block as indicated by A1 shown inFIG. 14, the data driver DRa latches the read image data based on thelatch signal LATa indicated by A3. The data driver DRa performs D/Aconversion of the latched image data, and outputs the data signal DATAacorresponding to the first read image data to the data signal outputline as indicated by A5.

When a wordline WL1 b of the memory block is selected and the secondimage data is read from the memory block as indicated by A2 shown inFIG. 14, the data driver DRb latches the read image data based on thelatch signal LATb indicated by A4. The data driver DRb performs D/Aconversion of the latched image data, and outputs the data signal DATAbcorresponding to the second read image data to the data signal outputline as indicated by A6.

As described above, each of the data drivers DRa and DRb outputs thedata signals for 30 data lines corresponding to 30 pixels so that thedata signals for 60 data lines corresponding to 60 pixels are output intotal.

A problem in which the width W of the integrated circuit device in thedirection D2 is increased due to an increase in the scale of the datadriver can be prevented by disposing (stacking) the data drivers DRa andDRb along the direction D1 as shown in FIG. 15. The data driver isconfigured in various ways depending on the type of display panel. Inthis case, the data drivers having various configurations can beefficiently disposed by disposing the data drivers along the directionD1. FIG. 15 shows the case where the number of data drivers disposed inthe direction D1 is two. However, the number of data drivers disposed inthe direction D1 may be three or more.

In FIG. 15, each of the data drivers DRa and DRb includes 30 (Q) drivercells DRC1 to DRC30 disposed along the direction D2. Each of the drivercells DRC1 to DRC30 receives image data for one pixel. Each of thedriver cells DRC1 to DRC30 performs D/A conversion of the image data forone pixel, and outputs a data signal corresponding to the image data forone pixel. Each of the driver cells DRC1 to DRC30 may include a datalatch circuit, the DAC (DAC for one pixel) shown in FIG. 10A, and theoutput section SQ shown in FIGS. 10B and 10C.

In FIG. 15, suppose that the number of pixels of the display panel inthe horizontal scan direction (the number of pixels in the horizontalscan direction driven by each integrated circuit device when a pluralityof integrated circuit devices cooperate to drive the data lines of thedisplay panel) is HPN, the number of data driver blocks (number of blockdivisions) is DBN, and the number of inputs of image data to the drivercell in one horizontal scan period is IN. The number of inputs IN isequal to the number of readings RN of image data in one horizontal scanperiod described with reference to FIG. 14. In this case, the number ofdriver cells DRC1 to DRC30 disposed along the direction D2 may beexpressed as “Q=HPN/(DBN×IN)”. In FIG. 15, since HPN=240, DBN=4, andIN=2, Q is 30 (240/(4×2)).

When the width (pitch) of the driver cells DRC1 to DR30 in the directionD2 is WD, the width WB (maximum width) of the first to Nth circuitblocks CB1 to CBN in the direction D2 may be expressed as“Q×WD≦WB<(Q+1)×WD”. When the width of the peripheral circuit section(e.g. row address decoder RD and interconnect region) included in thememory block in the direction D2 is WPC, “Q×WD≦WB<(Q+1)×WD+WPC” issatisfied.

Suppose that the number of pixels of the display panel in the horizontalscan direction is HPN, the number of bits of image data for one pixel isPDB, the number of memory blocks is MBN (=DBN), and the number ofreadings of image data from the memory block in one horizontal scanperiod is RN. In this case, the number (P) of sense amplifiers (senseamplifiers which output one bit of image data) arranged in a senseamplifier block SAB along the direction D2 may be expressed as“P=(HPN×PDB)/(MBN×RN)”. In FIG. 15, since HPN=240, PDB=18, MBN=4, andRN=2, P is 540 ((240×18)/(4×2)). The number P is the number of effectivesense amplifiers corresponding to the number of effective memory cells,and excludes the number of ineffective sense amplifiers for dummy memorycells and the like.

When the width (pitch) of each sense amplifier included in the senseamplifier block SAB in the direction D2 is WS, the width WSAB of thesense amplifier block SAB (memory block) in the direction D2 may beexpressed as “WSAB=P×WS”. When the width of the peripheral circuitsection included in the memory block in the direction D2 is WPC, thewidth WB (maximum width) of the circuit blocks CB1 to CBN in thedirection D2 may also be expressed as “P×WS≦WB<(P+PDB)×WS+WPC”.

5.4 Memory Cell

FIG. 16A shows a configuration example of the memory cell (SRAM)included in the memory block. The memory cell includes transfertransistors TRA1 and TRA2, load transistors TRA3 and TRA4, and drivertransistors TRA5 and TRA6. The transfer transistors TRA1 and TRA2 areturned ON when the wordline WL goes active, so that image data can bewritten into nodes NA1 and NA2 or read from the nodes NA1 and NA2. Theimage data written into the memory cell is held at the nodes NA1 and NA2by using flip-flop circuits formed by the transistors TRA3 to TRA6. Theconfiguration of the memory cell of the embodiment is not limited to theconfiguration shown in FIG. 16A. Various modifications and variationsmay be made, such as using resistor elements as the load transistorsTRA3 and TRA4 or adding other transistors.

FIGS. 16B and 16C show layout examples of the memory cell. FIG. 16Bshows a layout example of a horizontal type cell, and FIG. 16C shows alayout example of a vertical type cell. As shown in FIG. 16B, thehorizontal type cell is a cell in which the wordline WL is longer thanthe bitlines BL and XBL in each memory cell. As shown in FIG. 16C, thevertical type cell is a cell in which the bitlines BL and XBL are longerthan the wordline WL in each memory cell. The wordline WL shown in FIG.16C is a local wordline which is formed by a polysilicon layer andconnected with the transfer transistors TRA1 and TRA2. However, awordline formed by a metal layer may be further provided to prevent asignal delay in the wordline WL and to stabilize the potential of thewordline WL.

FIG. 17 shows an arrangement example of the memory block and the drivercell when using the horizontal type cell shown in FIG. 16B as the memorycell. FIG. 17 shows a section of the driver cell and the memory blockcorresponding to one pixel in detail.

As shown in FIG. 17, the driver cell DRC which receives image data forone pixel includes R (red), G (green), and B (blue) data latch circuitsDLATR, DLATG, and DLATB. Each of the data latch circuits DLATR, DLATG,and DLATB latches image data when the latch signal LAT (LATa, LATb) goesactive. The driver cell DRC includes the R, G, and B digital-analogconverters DACR, DACG, and DACB described with reference to FIG. 10A.The driver cell DRC also includes the output section SQ described withreference to FIGS. 10B and 10C.

A section of the sense amplifier block SAB corresponding to one pixelincludes R sense amplifiers SAR0 to SAR5, G sense amplifiers SAG0 toSAG5, and B sense amplifiers SAB0 to SAB5. The bitlines BL and XBL ofthe memory cells MC arranged along the direction D1 on the D1 side ofthe sense amplifier SAR0 are connected with the sense amplifier SAR0.The bitlines BL and XBL of the memory cells MC arranged along thedirection D1 on the D1 side of the sense amplifier SAR1 are connectedwith the sense amplifier SAR1. The above description also applies to therelationship between the remaining sense amplifiers and the memorycells.

When the wordline WL1 a is selected, image data is read from the memorycells MC of which the gate of the transfer transistor is connected withthe wordline WL1 a through the bitlines BL and XBL, and the senseamplifiers SAR0 to SAR5, SAG0 to SAG5, and SAB0 to SAB5 perform thesignal amplification operation. The data latch circuit DLATR latches6-bit R image data D0R to D5R from the sense amplifiers SAR0 to SAR5,the digital-analog converter DACR performs D/A conversion of the latchedimage data, and the output section SQ outputs the data signal DATAR. Thedata latch circuit DLATG latches 6-bit G image data D0G to D5G from thesense amplifiers SAG0 to SAG5, the digital-analog converter DACGperforms D/A conversion of the latched image data, and the outputsection SQ outputs the data signal DATAG. The data latch circuit DLATBlatches 6-bit G image data D0B to D5B from the sense amplifiers SAB0 toSAB5, the digital-analog converter DACB performs D/A conversion of thelatched image data, and the output section SQ outputs the data signalDATAB.

In the configuration shown in FIG. 17, the image data can be read aplurality of times in one horizontal scan period shown in FIG. 14 asdescribed below. Specifically, in the first horizontal scan period(first scan line select period), the first image data is read byselecting the wordline WL1 a, and the first data signal DATAa is outputas indicated by A5 shown in FIG. 14. In the first horizontal scanperiod, the second image data is read by selecting the wordline WL1 b,and the second data signal DATAb is output as indicated by A6 shown inFIG. 14. In the second horizontal scan period (second scan line selectperiod), the first image data is read by selecting the wordline WL2 a,and the first data signal DATAa is output. In the second horizontal scanperiod, the second image data is read by selecting the wordline WL2 b,and the second data signal DATAb is output. When using the horizontaltype cell, the image data can be read a plurality of times in onehorizontal scan period by selecting different wordlines (WL1 a and WL1b) in the memory block in one horizontal scan period.

FIG. 18 shows an arrangement example of the memory block and the drivercell when using the vertical type cell shown in FIG. 16C as the memorycell. The width of the vertical type cell in the direction D2 can bereduced in comparison with the horizontal type cell. Therefore, thenumber of memory cells in the direction D2 can be doubled in comparisonwith the horizontal type cell. When using the vertical type cell, thecolumn of the memory cells connected with each sense amplifier isswitched by using column select signals COLa and COLb.

In FIG. 18, when the column select signal COLa goes active, the columnCa side memory cells MC provided on the D1 side of the sense amplifiersSAR0 to SAR5 are selected and connected with the sense amplifiers SAR0to SAR5, for example. The signals of the image data stored in theselected memory cells MC are amplified and output as the image data D0Rto D5R. When the column select signal COLb goes active, the column Cbside memory cells MC provided on the D1 side of the sense amplifiersSAR0 to SAR5 are selected and connected with the sense amplifiers SAR0to SAR5. The signals of the image data stored in the selected memorycells MC are amplified and output as the image data D0R to D5R. Theabove description also applies to the read operation of image data fromthe memory cells connected with the remaining sense amplifiers.

In the configuration shown in FIG. 18, the image data can be read aplurality of times in one horizontal scan period shown in FIG. 14 asdescribed below. Specifically, in the first horizontal scan period, thefirst image data is read by selecting the wordline WL1 and setting thecolumn select signal COLa to active, and the first data signal DATAa isoutput as indicated by A5 shown in FIG. 14. In the first horizontal scanperiod, the second image data is read by again selecting the wordlineWL1 and setting the column select signal COLb to active, and the seconddata signal DATAb is output as indicated by A6 shown in FIG. 14. In thesecond horizontal scan period, the first image data is read by selectingthe wordline WL2 and setting the column select signal COLa to active,and the first data signal DATAa is output. In the second horizontal scanperiod, the second image data is read by again selecting the wordlineWL2 and setting the column select signal COLb to active, and the seconddata signal DATAb is output. When using the vertical type cell, theimage data can be read a plurality of times in one horizontal scanperiod by selecting a single wordline in the memory block a plurality oftimes in one horizontal scan period.

The configuration and the arrangement of the driver cell DRC are notlimited to those shown in FIGS. 17 and 18. Various modifications andvariations may be made. For example, when a low-temperature polysiliconTFT display driver or the like multiplexes and supplies R, G, and B datasignals to the display panel as shown in FIG 10C, R, G, and B image data(image data for one pixel) may be D/A converted by using one common DAC.In this case, it suffices that the driver cell DRC include one commonDAC having the configuration shown in FIG. 10A. In FIGS. 17 and 18, theR circuits (DLATR and DACR), the G circuits (DLATG and DACG), and the Bcircuits (DLATB and DACB) are disposed along the direction D2 (D4).However, the R, G, and B circuits may be disposed along the direction D1(D3).

6. Electronic Instrument

FIGS. 19A and 19B show examples of an electronic instrument(electro-optical device) including the integrated circuit device 10 ofthe embodiment. The electronic instrument may include constituentelements (e.g. camera, operation section, or power supply) other thanthe constituent elements shown in FIGS. 19A and 19B. The electronicinstrument of the embodiment is not limited to a portable telephone, andmay be a digital camera, PDA, electronic notebook, electronicdictionary, projector, rear-projection television, portable informationterminal, or the like.

In FIGS. 19A and 19B, a host device 410 is a microprocessor unit (MPU),a baseband engine (baseband processor), or the like. The host device 410controls the integrated circuit device 10 as a display driver. The hostdevice 410 may perform processing as an application engine and abaseband engine or processing as a graphic engine such as compression,decompression, or sizing. An image processing controller (displaycontroller) 420 shown in FIG. 19B performs processing as a graphicengine such as compression, decompression, or sizing instead of the hostdevice 410.

A display panel 400 includes a plurality of data lines (source lines), aplurality of scan lines (gate lines), and a plurality of pixelsspecified by the data lines and the scan lines. A display operation isrealized by changing the optical properties of an electro-opticalelement (liquid crystal element in a narrow sense) in each pixel region.The display panel 400 may be formed by an active matrix type panel usingswitch elements such as a TFT or TFD. The display panel 400 may be apanel other than an active matrix type panel, or may be a panel otherthan a liquid crystal panel.

In FIG. 19A, the integrated circuit device 10 may include a memory. Inthis case, the integrated circuit device 10 writes image data from thehost device 410 into the built-in memory, and reads the written imagedata from the built-in memory to drive the display panel. In FIG. 19B,the integrated circuit device 10 may not include a memory. In this case,image data from the host device 410 is written into a memory provided inthe image processing controller 420. The integrated circuit device 10drives the display panel 400 under control of the image processingcontroller 420.

Although only some embodiments of the invention have been described indetail above, those skilled in the art will readily appreciate that manymodifications are possible in the embodiments without departing from thenovel teachings and advantages of this invention. Accordingly, all suchmodifications are intended to be included within the scope of thisinvention. For example, any term (such as the output-side I/F region andthe input-side I/F region) cited with a different term having broader orthe same meaning (such as the first interface region and the secondinterface region) at least once in this specification or drawings can bereplaced by the different term in any place in this specification anddrawings. The configuration, arrangement, and operation of theintegrated circuit device and the electronic instrument are not limitedto those described in the embodiment. Various modifications andvariations may be made.

1. An integrated circuit device, comprising: first to Nth circuit blocks(N is an integer larger than one) disposed along a first direction, whenthe first direction is a direction from a first side of the integratedcircuit device toward a third side which is opposite to the first side,the first side being a short side, and when a second direction is adirection from a second side of the integrated circuit device toward afourth side which is opposite to the second side, the second side beinga long side, wherein the first to Nth circuit blocks include at leastone memory block which stores image data, and at least one data driverblock which drives data lines; and wherein the memory block and the datadriver block are disposed adjacent to each other along the firstdirection.
 2. The integrated circuit device as defined in claim 1,wherein the first to Nth circuit blocks include: first to Ith memoryblocks (I is an integer larger than one); and first to Ith data driverblocks respectively disposed adjacent to the first to Ith memory blocksalong the first direction.
 3. The integrated circuit device as definedin claim 2, wherein, when a direction opposite to the first direction isa third direction, a Jth data driver block (1≦J<I) among the first toIth data driver blocks is disposed adjacently on the third directionside of a Jth memory block among the first to Ith memory blocks; whereina (J+1)th memory block among the first to Ith memory blocks is disposedadjacently on the first direction side of the Jth memory block; andwherein a (J+1)th data driver block among the first to Ith data driverblocks is disposed adjacently on the first direction side of the (J+1)thmemory block.
 4. The integrated circuit device as defined in claim 3,wherein a column address decoder is used in common by the Jth memoryblock and the (J+1)th memory block.
 5. The integrated circuit device asdefined in claim 2, wherein, when a direction opposite to the firstdirection is a third direction, a Jth data driver block (1≦J<I) amongthe first to Ith data driver blocks is disposed adjacently on the thirddirecton side of a Jth memory block among the first to Ith memoryblocks; wherein a (J+1)th data driver block among the first to Ith datadriver blocks is disposed adjacently on the first direction side of theJth memory block; and wherein a (J+1)th memory block among the first toIth memory blocks is disposed adjacently on the first direction side ofthe (J+1)th data driver block.
 6. The integrated circuit device asdefined in claim 1, wherein wordlines connected to a memory cell of thememory block are disposed along the second direction in the memoryblock; and wherein bitlines through which image data stored in thememory block is output to the data driver block are disposed along thefirst direction in the memory block.
 7. The integrated circuit device asdefined in claim 1, wherein data signal output lines of the data driverblock are disposed along the second direction in the data driver block.8. The integrated circuit device as defined in claim 6, wherein datasignal output lines of the data driver block are disposed along thesecond direction in the data driver block.
 9. The integrated circuitdevice as defined in claim 1, wherein image data stored in the memoryblock is read from the memory block into the data driver block aplurality of times in one horizontal scan period.
 10. The integratedcircuit device as defined in claim 9, wherein the image data stored inthe memory block is read a plurality of times in one horizontal scanperiod by selecting different wordlines in the memory block in onehorizontal scan period.
 11. The integrated circuit device as defined inclaim 1, wherein the data driver block includes a plurality of datadrivers disposed along the first direction.
 12. The integrated circuitdevice as defined in claim 6, wherein the data driver block includes aplurality of data drivers disposed along the first direction.
 13. Theintegrated circuit device as defined in claim 1, wherein, when thenumber of pixels of a display panel in a horizontal scan direction isdenoted by HPN, the number of bits of image data for one pixel isdenoted by PDB, the number of the memory blocks is denoted by MBN, andthe number of readings of image data from the memory block in onehorizontal scan period is denoted by RN, a sense amplifier block of thememory block includes P sense amplifiers arranged along the seconddirection, P being the number of the sense amplifiers given by(HPN×PDB)/(MBN×RN).
 14. The integrated circuit device as defined inclaim 9, wherein, when the number of pixels of a display panel in ahorizontal scan direction is denoted by HPN, the number of bits of imagedata for one pixel is denoted by PDB, the number of the memory blocks isdenoted by MBN, and the number of readings of image data from the memoryblock in one horizontal scan period is denoted by RN, a sense amplifierblock of the memory block includes P sense amplifiers arranged along thesecond direction, P being the number of the sense amplifiers given by(HPN×PDB)/(MBN×RN).
 15. The integrated circuit device as defined inclaim 1, comprising: a first interface region provided along the fourthside and on the second direction side of the first to Nth circuitblocks; and a second interface region provided along the second side andon a fourth direction side of the first to Nth circuit blocks, thefourth direction being opposite to the second direction.
 16. Theintegrated circuit device as defined in claim 15, wherein data signaloutput lines of the data driver block are disposed in the firstinterface region along the first direction.
 17. An electronicinstrument, comprising: the integrated circuit device as defined inclaim 1; and a display panel driven by the integrated circuit device.18. An electronic instrument, comprising: the integrated circuit deviceas defined in claim 6; and a display panel driven by the integratedcircuit device.
 19. An electronic instrument, comprising: the integratedcircuit device as defined in claim 9; and a display panel driven by theintegrated circuit device.
 20. An electronic instrument, comprising: theintegrated circuit device as defined in claim 15; and a display paneldriven by the integrated circuit device.